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| ? freescale semiconductor, inc., 2004, 2004, 2006. all rights reserved. freescale semiconductor technical data the mpc8541e integrates a powerpc? processor core built on power architecture? technology with system logic required for networking, tel ecommunications, and wireless infrastructure applications. the mpc8541e is a member of the powerquicc? iii family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the power architecture technology. for functional characteristics of the processor, refer to the mpc8555e powerquicc? iii integrated communications processor reference manual . to locate any published errata or updates for this document refer to http://www.freescale.c om or contact your freescale sales office. mpc8541eec rev. 4, 12/2006 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. ethernet: three-speed, mii management . . . . . . . . . . 20 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. cpm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12. i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14. package and pin listings . . . . . . . . . . . . . . . . . . . . . . . 53 15. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 16. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17. system design information . . . . . . . . . . . . . . . . . . . . . 75 18. document revision history . . . . . . . . . . . . . . . . . . . . 82 19. device nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 82 mpc8541e powerquicc? iii integrated communications processor hardware specifications
mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 2 freescale semiconductor overview 1 overview the following section provides a high-le vel overview of the mpc8541e features. figure 1 shows the major functional units within the mpc8541e. . figure 1. mpc8541e block diagram 1.1 key features the following lists an overview of the mpc8541e feature set. ? embedded e500 book e-compatible core ? high-performance, 32-bit book e-enhanced core that implements the powerpc architecture ? dual-issue superscalar, 7-stage pipeline design ? 32-kbyte l1 instruction cache and 32-kbyt e l1 data cache with parity protection ? lockable l1 caches?entire cache or on a per-line basis ? separate locking for instructions and data ? single-precision floa ting-point operations ? memory management unit especially designed for embedded applications ? enhanced hardware and software debug support ? dynamic power management ? performance monitor facility i 2 c controller local bus controller 64/32b pci controller 0/32b pci controller dma controller 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis serial dma rom i-memory dpram risc engine parallel i/o baud rate generators timers fcc fcc spi i2c serial interfaces miis/rmiis i/os cpm ddr sdram controller cpm controller interrupt 256 kbyte l2 cache/ sram e500 core 32-kbyte l1 i cache 32-kbyte l1 d cache core complex e500 coherency module ocean irqs sdram ddr gpio 32b programmable interrupt controller bus duart security engine mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 3 overview ? security engine is optimized to handle all the algorithms associat ed with ipsec, ssl/tls, srtp, 802.11i, iscsi, and ike processing. the security engine contains 4 crypto-channels, a controller, and a set of crypto execution units (eus). the execution units are: ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048-bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511-bits ? data encryption standard execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits.two key ? ecb, cbc, ccm, a nd counter modes ? arc four execution unit (afeu) ? implements a stream cipher comp atible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160-bit or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? random number generator (rng) ? 4 crypto-channels, each supporting multi-command descriptor chains ? static and/or dynamic assignment of crypto- execution units via an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? high-performance risc cpm ? two full-duplex fast communications controllers (fccs) that support th e following protocol: ? ieee802.3/fast ethernet (10/100) ? serial peripheral interface (spi ) support for master or slave ?i 2 c bus controller ? general-purpose parallel ports?16 parallel i/o lines with interrupt capability ? 256 kbytes of on-chip memory ? can act as a 256- kbyte level-2 cache ? can act as a 256-kbyte or two 128- kbyte memory-mapped sram arrays ? can be partitioned into 128-k byte l2 cache plus 128-kbyte sram ? full ecc support on 64-bit boundary in both cache and sram modes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 4 freescale semiconductor overview ? sram operation supports reloca tion and is byte-accessible ? cache mode supports instructi on caching, data caching, or both ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing) ? eight-way set-associative cache organi zation (1024 sets of 32-byte cache lines) ? supports locking the entire cache or selected lines ? individual line locks set and cleared through b ook e instructions or by externally mastered transactions ? global locking and flash cl earing done through writes to l2 configuration registers ? instruction and data locks can be flash cleared separately ? read and write buffering for internal bus accesses ? address translation and mapping unit (atmu) ? eight local access windows define mappi ng within local 32-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a c onfiguration window on pci ? four inbound windows ? four outbound windows plus default translation for pci ? ddr memory controller ? programmable timing supporti ng first generation ddr sdram ? 64-bit data interface, up to mhz data rate ? four banks of memory supported, each up to 1 gbyte ? dram chip configurations from 64 mb its to 1 gbit with x8/x16 data ports ? full ecc support ? page mode support (up to 16 simultaneous open pages) ? contiguous or discontiguous memory mapping ? sleep mode support for self refresh ddr sdram ? supports auto refreshing ? on-the-fly power manage ment using cke signal ? registered dimm support ? fast memory access via jtag port ? 2.5-v sstl2 compatible i/o ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interrupt controller such as the 8259 programmable interrupt controller mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 5 overview ? four global high resolution timers/count ers that can generate interrupts ? supports additional internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to exte rnal pin for external processing ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs ? interrupt summary registers allow fa st identification of interrupt source ?two i 2 c controllers (one is c ontained within the cpm, the other is a stand-alone controller which is not part of the cpm) ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configurati on data from serial rom at reset via the stand-alone i 2 c interface ? can be used to initialize conf iguration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 166 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are cont rolled by an on-chip memory controller ? three protocol engines availabl e on a per chip select basis: ? general purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with conf igurable bus width (8-, 16-, or 32-bit) ? two three-speed (10/100/1000)et hernet controllers (tsecs) ? dual ieee 802.3, 802.3u, 802.3x, 802.3z ac compliant controllers ? support for ethernet physical interfaces: ? 10/100/1000 mbps ieee 802.3 gmii ? 10/100 mbps ieee 802.3 mii ? 10 mbps ieee 802.3 mii mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 6 freescale semiconductor overview ? 1000 mbps ieee 802.3z tbi ? 10/100/1000 mbps rgmii/rtbi ? full- and half-duplex support ? buffer descriptors are backwards comp atible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? 2-kbyte internal transmit and receive fifos ? mii management interface for control and status ? programmable crc ge neration and checking ? ocean switch fabric ? three-port crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with pa yloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by bot h local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segm ent, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enfor ced coherency (snoop/no-snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ? pci controllers ? pci 2.2 compatible ? one 64-bit or two 32-bit pci ports supported at 16 to 66 mhz ? host and agent mode support, 64- bit pci port can be host or agen t, if two 32-bit ports, only one can be an agent ? 64-bit dual address cycle (dac) support ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to -pci and pci-to -memory writes ? pci 3.3-v compatible mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 7 electrical characteristics ? selectable hardware-enforced coherency ? selectable clock source (sys clk or independent pci_clk) ? power management ? fully static 1.2-v cmos de sign with 3.3- and 2.5-v i/o ? supports power save mode s: doze, nap, and sleep ? employs dynamic power management ? selectable clock source (sys clk or independent pci_clk) ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quant ity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit stre aming of entire block for fast upload and download ? ieee 1149.1-compliant, jtag boundary scan ? 783 fc-pbga package 2 electrical characteristics this section provides the ac and dc electrical sp ecifications and thermal characteristics for the mpc8541e. the mpc8541e is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 8 freescale semiconductor electrical characteristics 2.1 overall dc electrical characteristics this section covers the ratings, c onditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.32 0.3 to 1.43 (for 1 ghz only) v pll supply voltage av dd ?0.3 to 1.32 0.3 to 1.43 (for 1 ghz only) v ddr dram i/o voltage gv dd ?0.3 to 3.63 v three-speed ethernet i/o, mii management voltage lv dd ?0.3 to 3.63 ?0.3 to 2.75 v cpm, pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v 3 input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 5 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4, 5 cpm, local bus, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3)1 v 5 pci ov in ?0.3 to (ov dd + 0.3) v 6 storage temperature range t stg ?55 to 150 ?c notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: lv in must not exceed lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 3. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 9 electrical characteristics 2.1.2 power sequencing the mpc8541erequires its power rails to be a pplied in a specific se quence in order to ensure proper device operation. these requirements ar e as follows for power up: 1. v dd , av dd n 2. gv dd , lv dd , ov dd (i/o supplies) items on the same line have no ordering requirement wi th respect to one another. items on separate lines must be ordered sequentially such th at voltage rails on a prev ious step must reach 90 percent of their value before the voltage rails on the current step r each ten percent of theirs. note if the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment. note from a system standpoint, if the i/o power supplies ramp prior to the vdd core supply, the i/os on the mpc8541e may drive a logic one or zero during power-up. 2.1.3 recommended operating conditions table 2 provides the recommended operating conditions for the mpc8541e. note that the values in table 2 are the recommended and tested operating conditions. proper devi ce operation outside of these conditions is not guaranteed. table 2. recommended operating conditions characteristic symbol recommended value unit core supply voltage v dd 1.2 v 60 mv 1.3 v 50 mv (for 1 ghz only) v pll supply voltage av dd 1.2 v 60 mv 1.3 v 50 mv (for 1 ghz only) v ddr dram i/o voltage gv dd 2.5 v 125 mv v three-speed ethernet i/o voltage lv dd 3.3 v 165 mv 2.5 v 125 mv v pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 165 mv v mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 10 freescale semiconductor electrical characteristics figure 2 shows the undershoot and overshoot voltages at the in terfaces of the mpc8541e. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd the mpc8541e core voltage must alwa ys be provided at nominal 1.2 v (see table 2 for actual recommended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provi ded at the voltages shown in table 2 . the input voltage th reshold scales with respect to the associat ed i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram interface uses a single-ended differential receiver re ferenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the ss tl2 electrical signaling standard. input voltage ddr dram signals mv in gnd to gv dd v ddr dram reference mv ref gnd to gv dd v three-speed ethernet signals lv in gnd to lv dd v pci, local bus, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in gnd to ov dd v die-junction temperature t j 0 to 105 c table 2. recommended operating conditions (continued) characteristic symbol recommended value unit gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t sys 1 1. note that t sys refers to the clock period a ssociated with t he sysclk signal. v ih v il note: mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 11 power characteristics 2.1.4 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 3 power characteristics the estimated typical power dissip ation for this family of power quicc iii devices is shown in table 4 . table 3. output drive capability driver type programmable output impedance ( ) supply voltag e notes local bus interface utilities signals 25 ov dd = 3.3 v 1 42 (default) pci signals 25 2 42 (default) ddr signal 20 gv dd = 2.5 v tsec/10/100 signals 42 lv dd = 2.5/3.3 v duart, system contro l, i2c, jtag 42 ov dd = 3.3 v notes: 1. the drive strength of the local bus interface is determined by the configuration of the app ropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt1 signal at reset. table 4. power dissipation (1) (2) notes: 1. the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd .. 2. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, am bient temperature, air flow, power dissipation of other components on the board, and board therma l resistance. any customer design must take these considerations into account to ensure the maximum 105 degrees junction temperature is not exceeded on this device. ccb frequency (mhz) core frequency (mhz) v dd typical power (3)(4) (w) maximum power (5) (w) 200 400 1.2 4.4 6.1 500 1.2 4.7 6.5 600 1.2 5.0 6.8 267 533 1.2 4.9 6.7 667 1.2 5.4 7.2 800 1.2 5.8 8.6 333 667 1.2 5.5 7.4 833 1.2 6.0 8.8 1000 (6) 1.3 9.0 12.2 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 12 freescale semiconductor power characteristics 3. typical power is based on a nominal voltage of v dd = 1.2v, a nominal process, a junction temperature of t j = 105 c, and a dhrystone 2.1 benchmark application. 4. thermal solutions will likely need to design to a value higher than typical power based on the end application, t a target, and i/o power. 5. maximum power is based on a nominal voltage of v dd = 1.2v, worst case process, a junction temperature of t j = 105 c, and an artificial smoke test. 6. the nominal recommended v dd = 1.3v for this speed grade. table 5. typical i/o power dissipation interface parameters gvdd (2.5v) ovdd (3.3v) lvdd (3.3v) lvdd (2.5v) unit comments ddr i/o ccb = 200 mhz 0.46 w ? ccb = 266 mhz 0.59 w ? ccb = 300 mhz 0.66 w ? ccb = 333 mhz 0.73 w ? pci i/o 64b, 66mhz 0.14 w ? 64b, 33mhz 0.08 w ? 32b, 66mhz 0.07 w multiply by 2 if using two 32b ports 32b, 33mhz 0.04 w local bus i/o 32b, 167mhz 0.30 w ? 32b, 133mhz 0.24 w ? 32b, 83mhz 0.16 w 32b, 66mhz 0.13 w ? 32b, 33mhz 0.07 w ? tsec i/o mii 0.01 w multiply by number of interfaces used. gmii or tbi 0.07 w rgmii or rtbi 0.04 w cpm - fcc mii 0.015 w ? rmii 0.013 w ? hdlc 16 mbps 0.009 w ? mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 13 clock timing 4 clock timing 4.1 system clock timing table 6 provides the system clock (sysclk) ac timing specificati ons for the mpc8541e. 4.2 tsec gigabit reference clock timing table 7 provides the tsec gigabit reference clock (ec_ gtx_clk125) ac timing specifications for the mpc8541e. table 6. sysclk ac ti ming specif ications parameter/condition symbol min typical max unit notes sysclk frequency f sysclk ? ? 166 mhz 1 sysclk cycle time t sysclk 6.0 ? ? ns ? sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns 2 sysclk duty cycle t khk /t sysclk 40 ? 60 % 3 sysclk jitter ? ? ? +/- 150 ps 4, 5 notes: 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio se ttings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for sysclk are measured at 0.6 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. for spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 khz of modulation regardless of the input frequency. table 7. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ec_gtx_clk125 frequency f g125 ? 125 ? mhz ec_gtx_clk125 cycle time t g125 ?8?ns ec_gtx_clk125 rise time t g125r ??1.0ns1 ec_gtx_clk125 fall time t g125f ??1.0ns1 ec_gtx_clk125 duty cycle gmii, tbi rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %1, 2 notes: 1. timing is guaranteed by design and characterization. 2. ec_gtx_clk125 is used to generate gtx clock for tsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as phy device can to lerate the duty cycle generated by gtx_clk of tsec. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 14 freescale semiconductor reset initialization 4.3 real time clock timing table 8 provides the real time clock (rtc) ac timing specifications. 5 reset initialization this section describes the ac elec trical specifications for the reset initialization timing requirements of the mpc8541e. table 9 provides the reset initializa tion ac timing specifications. table 10 provides the pll and dll lock times. table 8. rtc ac timing specifications parameter/condition symbol min typical max unit notes rtc clock high time t rtch 2 x t ccb_clk ??ns rtc clock low time t rtcl 2 x t ccb_clk ??ns table 9. reset initializati on timing sp ecifications parameter/condition min max unit notes required assertion time of hreset 100 ? s minimum assertion time for sreset 512 ? sysclks 1 pll input setup time with stable sysclk before hreset negation 100 ? s input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 notes: 1. sysclk is identical to the pci_clk signal and is the primary clock input for the mpc8541e. see the mpc8555e powerquicc? iii integrated communications processor reference manual for more details. table 10. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s dll lock times 7680 122,880 ccb clocks 1, 2 notes: 1. dll lock times are a function of the ratio between the output clock and the platform (or ccb) clock. a 2:1 ratio results in t he minimum and an 8:1 ratio results in the maximum. 2. the ccb clock is de termined by the sysclk platform pll ratio. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 15 ddr sdram 6 ddr sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8541e. 6.1 ddr sdram dc electrical characteristics table 11 provides the recommended ope rating conditions for the ddr sdram component(s) of the mpc8541e. table 12 provides the dd r capacitance. table 11. ddr sdram dc electrical characteristics parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.18 gv dd + 0.3 v input low voltage v il ?0.3 mv ref ? 0.18 v output leakage current i oz ?10 10 a4 output high current (v out = 1.95 v) i oh ?15.2 ? ma output low current (v out = 0.35 v) i ol 15.2 ? ma mv ref input leakage current i vref ?5 a notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 12. ddr sdram capacitance parameter/condition symbol min max unit notes input/output capacitance : dq, dqs, msync_in c io 68pf1 delta input/output ca pacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak to peak) = 0.2 v. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 16 freescale semiconductor ddr sdram 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical ch aracteristics for the ddr sdram interface. 6.2.1 ddr sdram input ac timing specifications table 13 provides the input ac ti ming specifications for the ddr sdram interface. 6.2.2 ddr sdram output ac timing specifications table 14 and table 15 provide the output ac timing specifica tions and measurement conditions for the ddr sdram interface. table 13. ddr sdram input ac timing specifications at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 gv dd + 0.3 v mdqs?mdq/mecc input skew per byte for ddr = 333 mhz for ddr < 266 mhz t diskew ? 750 1125 ps 1 note: 1. maximum possible skew between a data strobe (mdqs[n]) and an y corresponding bit of data (mdq[8n + {0...7}] if 0 <= n <= 7) or ecc (mecc[{0...7}] if n = 8). table 14. ddr sdram output ac timing specifications for source synchronous mode at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) t mck 610ns2 skew between any mck to addr/cmd 333 mhz 266 mhz 200 mhz t aoskew -1000 -1100 -1200 200 300 400 ps 3 addr/cmd output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhas 2.8 3.45 4.6 ?ns4 addr/cmd output hold with respect to mck 333 mhz 266 mhz 200 mhz t ddkhax 2.0 2.65 3.8 ?ns4 mcs (n) output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcs 2.8 3.45 4.6 ?ns4 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 17 ddr sdram mcs (n) output hold with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcx 2.0 2.65 3.8 ?ns4 mck to mdqs 333 mhz 266 mhz 200 mhz t ddkhmh -0.9 -1.1 -1.2 0.3 0.5 0.6 ns 5 mdq/mecc/mdm output setup with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhds, t ddklds 900 900 1200 ?ps6 mdq/mecc/mdm output hold with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhdx, t ddkldx 900 900 1200 ?ps6 mdqs preamble start t ddkhmp -0.5 t mck ? 0.9 -0.5 t mck +0.3 ns 7 mdqs epilogue end t ddklme -0.9 0.3 ns 7 notes: 1. the symbols used for timing specif ications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d ) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. in the source synchronous mode, mck/mck can be shifted in 1/4 applied cycle increments through the clock control register. for the skew measurements referenced for t aoskew it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of mck. 4. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assumed that the clock control regist er is set to adjust the memory clocks by 1/2 applied cycle. the mcsx pins are separated from t he addr/cmd (address and command) bus in the hw spec. this was separated because the mcsx pins typically have differen t loadings than the rest of the address and command bus, even though they have the same timings. 5. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). in the source synchronous mode, mdqs can launch later than mck by 0.3 ns at the maximum. however, mck may launch later than mdqs by as much as 0.9 ns. t ddkhmh can be modified through control of the dqss overri de bits in the timing_cfg_2 register. in source synchronous mode, this will typically be set to the same dela y as the clock adjust in th e clk_cntl register. the timing parameters listed in the table assume that these two parame ters have been set to the same adjustment value. see the mpc8555e powerquicc? iii integrated communications processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 6. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data st robe should be centered inside of the da ta eye at the pins of the mpc8541e. 7. all outputs are referenced to the rising edge of mc k(n) at the pins of t he mpc8541e. note that t ddkhmp follows the symbol conventions described in note 1. table 14. ddr sdram output ac timing specificat ions for source synchr onous mode (c ontinued) at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 18 freescale semiconductor ddr sdram figure 3 shows the ddr sdram output timing for a ddress skew with respect to any mck. figure 3. timing diagram for t aoskew measurement figure 4 shows the ddr sdram output timing diag ram for the source synchronous mode. figure 4. ddr sdram output timing diagram for source synchronous mode addr/cmd mck [n] mck[n] t mck t aoskewmax) cmd noop t aoskew(min) addr/cmd cmd noop addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddklme t ddkhmp mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 19 duart figure 5 provides the ac test load for the ddr bus. figure 5. ddr ac test load 7duart this section describes the dc and ac electrical specifications for the duart interface of the mpc8541e. 7.1 duart dc electrical characteristics table 16 provides the dc electrical characteristics for the duart interface of the mpc8541e. table 15. ddr sdram measurement conditions symbol ddr unit notes v th mv ref 0.31 v v 1 v out 0.5 gv dd v2 notes: 1. data input threshold measurement point. 2. data output measurement point. table 16. duart dc electrical characteristics parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v input current i in v in 1 = 0 v or v in = v dd ?5 a high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a? 0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta bl e 2 . output z 0 = 50 gv dd /2 r l = 50 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 20 freescale semiconductor ethernet: three-speed, mii management 7.2 duart ac electrical specifications table 17 provides the ac timing parameters fo r the duart interface of the mpc8541e. 8 ethernet: three-speed, mii management this section provides the ac and dc electrical characteristics forthree-speed, 10/100/1000, and mii management. 8.1 three-speed ethernet controller (tsec) (10/100/1000 mbps)?gmii/mii/t bi/rgmii/rtbi electrical characteristics the electrical characteristi cs specified here apply to allgmii (gig abit media independent interface), the mii (media independent interface), tbi (ten-bit in terface), rgmii (reduced gigabit media independent interface), and rtbi (reduced ten-bi t interface) signals ex cept mdio (management data input/output) and mdc (management data clock). the rgmii and rtbi interfaces are defined fo r 2.5 v, while the gmii and tbi interfaces can be ope rated at 3.3 or 2.5 v. whether thegmii, mii, or tbi interface is operated at 3.3 or 2.5 v, the timi ng is compliant with the ieee 802.3 standar d. the rgmii and rtbi interfaces follow the hewlett-packard reduced pin-count interface for gigabit ethernet p hysical layer device specification version 1.2a (9/22/2000). the electrical characte ristics for mdio and mdc are specified in section 8.3, ?ethernet management interf ace electrical characteristics .? 8.1.1 tsec dc electrical characteristics all gmii, mii, tbi, rgmii, and rt bi drivers and receivers comply wi th the dc parametric attributes specified in table 18 and table 19 . the potential applied to the input of a gmii, mii, tbi, rgmii, or rtbi receiver may exceed the potential of the receiv er?s power supply (i.e., a gmii driver powered from a 3.6-v supply driving v oh into a gmii receiver powered from a 2.5-v supply). tolerance for dissimilar gmii driver and receiver supply poten tials is implicit in these specifi cations. the rgmii and rtbi signals are based on a 2.5-v cmos interface vol tage as defined by jedec eia/jesd8-5. table 17. duart ac timing specifications parameter value unit notes minimum baud rate f ccb_clk / 1048576 baud 3 maximum baud rate f ccb_clk / 16 baud 1, 3 oversample rate 16 ? 2, 3 notes: 1. actual attainable baud rate will be limit ed by the latency of interrupt processing. 2. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. 3. guaranteed by design. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 21 ethernet: three-speed, mii management table 18. gmii, mii, and tbi dc electrical characteristics parameter symbol con ditions min max unit supply voltage 3.3 v lv dd ?3.133.47v output high voltage v oh i oh = ?4.0 ma lv dd = min 2.40 lv dd + 0.3 v output low voltage v ol i ol = 4.0 ma lv dd = min gnd 0.50 v input high voltage v ih ? ? 1.70 lv dd + 0.3 v input low voltage v il ? ? ?0.3 0.90 v input high current i ih v in 1 = lv dd ?40 a input low current i il v in 1 = gnd ?600 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . table 19. gmii, mii, rgmii rtbi, and tbi dc electrical characteristics parameters symbol min max unit supply voltage 2.5 v lv dd 2.37 2.63 v output high voltage (lv dd = min, i oh = ?1.0 ma) v oh 2.00 lv dd + 0.3 v output low voltage (lv dd = min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v input high voltage (lv dd = min) v ih 1.70 lv dd + 0.3 v input low voltage (lv dd = min) v il ?0.3 0.70 v input high current (v in 1 = lv dd ) i ih ?10 a input low current (v in 1 = gnd) i il ?15 ? a note: 1. note that the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta b l e 2 . mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 22 freescale semiconductor ethernet: three-speed, mii management 8.2 gmii, mii, tbi, rgmii, an d rtbi ac timing specifications the ac timing specifications for gm ii, mii, tbi, rgmii, and rtbi are presented in this section. 8.2.1 gmii ac timing specifications this section describes the gmii transm it and receive ac timing specifications. 8.2.2 gmii transmit ac timing specifications table 20 provides the gmii transmit ac timing specifications. figure 6 shows the gmii transm it ac timing diagram. figure 6. gmii transmit ac timing diagram table 20. gmii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t gtx ?8.0? ns gtx_clk duty cycle t gtxh /t gtx 40 ? 60 % gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ? ? ns gtx_clk to gmii data txd[7: 0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise and fall times t gtxr 3 , t gtxr 2,4 ??1.0ns notes: 1. the symbols used for timing specific ations herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol repres entation is based on three letter s representing the clock of a particular functional. for ex ample, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appr opriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by characterization. 4. guaranteed by design. gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 23 ethernet: three-speed, mii management 8.2.2.1 gmii receive ac timing specifications table 21 provides the gmii receiv e ac timing specifications. figure 7 provides the ac test load for tsec. figure 7. tsec ac test load figure 8 shows the gmii receive ac timing diagram. figure 8. gmii receive ac timing diagram table 21. gmii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 % rxd[7:0], rx_dv, rx_er se tup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns rx_clk clock rise and fall time t grxr , t grxf 2,3 ??1.0ns note: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock referenc e symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used wit h the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 24 freescale semiconductor ethernet: three-speed, mii management 8.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.3.1 mii transmit ac timing specifications table 22 provides the mii transmit ac timing specifications. figure 9 shows the mii transmit ac timing diagram. figure 9. mii transmit ac timing diagram 8.2.3.2 mii receive ac timing specifications table 23 provides the mii receive ac timing specifications. table 22. mii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx 2 ?400? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise and fall time t mtxr , t mtxf 2,3 1.0 ? 4.0 ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol represent ation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with th e appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 25 ethernet: three-speed, mii management notes: 1. the symbols used for timing specific ations herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input si gnals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (g r) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol represent ation is based on three lett ers representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. figure 10 shows the mii receive ac timing diagram. figure 10. mii receive ac timing diagram table 23. mii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx 2 ?400? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise and fall time t mrxr , t mrxf 2,3 1.0 ? 4.0 ns rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 26 freescale semiconductor ethernet: three-speed, mii management 8.2.4 tbi ac timing specifications this section describes the tbi transmit and receive ac ti ming specifications. 8.2.4.1 tbi transmit ac timing specifications table 24 provides the mii transmit ac timing specifications. figure 11 shows the tbi transmit ac timing diagram. figure 11. tbi transmit ac timing diagram table 24. tbi transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t ttx ?8.0? ns gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % gmii data tcg[9:0], tx_er, tx_en setup time gtx_clk going high t ttkhdv 2.0 ? ? ns gmii data tcg[9:0], tx_er, tx_en hold time from gtx_clk going high t ttkhdx 1.0 ? ? ns gtx_clk clock rise and fall time t ttxr , t ttxf 2,3 ??1.0ns notes: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) r each the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) cloc k. for rise and fall times, the latter convention is used with the appropriat e letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. gtx_clk tcg[9:0] t ttxr t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx t ttxf mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 27 ethernet: three-speed, mii management 8.2.4.2 tbi receive ac timing specifications table 25 provides the tbi receive ac timi ng specifications. figure 12 shows the tbi receive ac timing diagram. figure 12. tbi receive ac timing diagram table 25. tbi receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period t trx 16.0 ns rx_clk skew t sktrx 7.5 ? 8.5 ns rx_clk duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising rx_clk t trdxkh 1.5 ? ? ns rx_clk clock rise time and fall time t trxr , t trxf 2,3 0.7 ? 2.4 ns note: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representat ion is based on three letters representing the clock of a particular functional. for ex ample, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. rx_clk1 rxd[9:0] t trx t trxh t trxr t trxf t trdvkh rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 28 freescale semiconductor ethernet: three-speed, mii management 8.2.5 rgmii and rtbi ac timing specifications table 26 presents the rgmii and rt bi ac timing specifications. table 26. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt 5 ?500 0 500 ps data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock cycle duration 3 t rgt 6 7.2 8.0 8.8 ns duty cycle for 1000base-t 4 t rgth /t rgt 6 45 50 55 % duty cycle for 10base-t and 100base-tx 3 t rgth /t rgt 6 40 50 60 % rise and fall times t rgtr 6,7 , t rgtf 6,7 ? ? 0.75 ns notes: 1. note that, in general, the clock reference symbol representatio n for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (r x) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbo l that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. the rgmii specification requires that pc boa rd designer add 1.5 ns or greater in trac e delay to the rx_clk in order to meet this specification. however, as stated above, this device will function with only 1.0 ns of delay. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk duri ng speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. guaranteed by characterization. 6. guaranteed by design. 7. signal timings are measured at 0.5 v and 2.0 v voltage levels. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 29 ethernet: three-speed, mii management figure 13 shows the rbmii and rtbi ac timing and multiplexing diagrams. figure 13. rgmii and rtbi ac timing and multiplexing diagrams 8.3 ethernet management interface electrical characteristics the electrical characteristics sp ecified here apply to mii mana gement interface signals mdio (management data input/output) and mdc (management data clock). th e electrical characteristics for gmii, rgmii, tbi and rtbi are specified in section 8.1, ?three-speed ethernet controller (tsec) (10/100/1000 mbps)?gmii/mii/t bi/rgmii/rtbi electrical characteristics.? 8.3.1 mii management dc electrical characteristics the mdc and mdio are defined to ope rate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 27 . table 27. mii management dc electrical characteristics parameter symbol conditions min max unit supply voltage (3.3 v) ov dd ? 3.13 3.47 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.10 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd 0.50 v input high voltage v ih ?1.70?v input low voltage v il ??0.90v gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 30 freescale semiconductor ethernet: three-speed, mii management 8.3.2 mii management ac electrical specifications table 28 provides the mii management ac timing specifications. input high current i ih lv dd = max v in 1 = 2.1 v ? 40 a input low current i il lv dd = max v in = 0.5 v ?600 ? a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta bl e 2 . table 28. mii management ac timing specifications at recommended operating conditions with lv dd is 3.3 v 5%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc 0.893 ? 10.4 mhz 2 mdc period t mdc 96 ? 1120 ns mdc clock pulse width high t mdch 32 ? ? ns mdc to mdio valid t mdkhdv 2*[1/(f ccb_clk /8)] ns 3 mdc to mdio delay t mdkhdx 10 ? 2*[1/(f ccb_clk /8)] ns 3 mdio to mdc setup time t mddvkh 5? ?ns mdio to mdc hold time t mddxkh 0? ?ns mdc rise time t mdcr ? ? 10 ns mdc fall time t mdhf ? ? 10 ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the system clock speed (that is, for a system clock of 267 mhz, the delay is 70 ns and for a system clock of 333 mhz, the delay is 58 ns). 3. this parameter is dependent on the ccb clock speed (that is, for a ccb clock of 267 mhz, the delay is 60 ns and for a ccb clock of 333 mhz, the delay is 48 ns). 4. guaranteed by design. table 27. mii management dc electrical characteristics (continued) parameter symbol conditions min max unit mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 31 local bus figure 14 shows the mii management ac timing diagram. figure 14. mii management interface timing diagram 9 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8541e. 9.1 local bus dc electrical characteristics table 29 provides the dc electrical characteristics for the local bus interface. table 29. local bus dc electrical characteristics parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v input current i in v in 1 = 0 v or v in = v dd ?5 a high-level output voltage v oh ov dd = min, i oh = -2ma ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 2ma ? 0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output) mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 32 freescale semiconductor local bus 9.2 local bus ac electrical specifications table 30 describes the general timing parameters of the local bus interface of the mpc8541e with the dll enabled. table 30. local bus general timing parameters - dll enabled parameter configuration 7 symbol 1 min max unit notes local bus cycle time t lbk 6.0 ? ns 2 lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 9 input setup to loca l bus clock (except lupwait) t lbivkh1 1.8 ? ns 3, 4, 8 lupwait input setup to local bus clock t lbivkh2 1.7 ? ns 3, 4 input hold from loca l bus clock (except lupwait) t lbixkh1 0.5 ? ns 3, 4, 8 lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) lwe[0:1] = 00 t lbkhov1 ? 2.3 ns 3, 8 lwe[0:1] = 11 (default) 3.8 local bus clock to data valid for lad/ldp lwe[0:1] = 00 t lbkhov2 ? 2.5 ns 3, 8 lwe[0:1] = 11 (default) 4.0 local bus clock to address valid for lad lwe[0:1] = 00 t lbkhov3 ? 2.6 ns 3, 8 lwe[0:1] = 11 (default) 4.1 output hold from local bus clock (except lad/ldp and lale) lwe[0:1] = 00 t lbkhox1 0.7 ? ns 3, 8 lwe[0:1] = 11 (default) 1.6 output hold from local bus clock for lad/ldp lwe[0:1] = 00 t lbkhox2 0.7 ? ns 3, 8 lwe[0:1] = 11 (default) 1.6 local bus clock to output high impedance (except lad/ldp and lale) lwe[0:1] = 00 t lbkhoz1 ? 2.8 ns 5, 9 lwe[0:1] = 11 (default) 4.2 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 33 local bus table 31 describes the general timing parameters of the local bus interface of the mpc8541e with the dll bypassed. local bus clock to output high impedance for lad/ldp lwe[0:1] = 00 t lbkhoz2 ? 2.8 ns 5, 9 lwe[0:1] = 11 (default) 4.2 notes: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for dll enabled mode. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in for dll enabled to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. the value of t lbotot is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by lbcr[ahd], and the number of local bus buffer delays used as programmed at po wer-on reset with configuration pins lwe[0:1] . 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at ov dd /2. 8. guaranteed by characterization. 9. guaranteed by design. table 31. local bus general timing parameters - dll bypassed parameter configuration 7 symbol 1 min max unit notes local bus cycle time t lbk 6.0 ? ns 2 internal launch/capture clock to lclk delay t lbkhkt 1.8 3.4 ns 8 lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 9 input setup to local bus clock (except lupwait) t lbivkh1 5.2 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 5.1 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 -1.3 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 -0.8 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) lwe[0:1] = 00 t lbklov1 ?0.5ns 3 lwe[0:1] = 11 (default) 2.0 local bus clock to data valid for lad/ldp lwe[0:1] = 00 t lbklov2 ?0.7ns 3 lwe[0:1] = 11 (default) 2.2 table 30. local bus general timing parameters - dll enabled (continued) parameter configuration 7 symbol 1 min max unit notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 34 freescale semiconductor local bus notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go inva lid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for dll enabled mode. 3. all signals are measured from ov dd /2 of the rising edge of local bus clock for dll bypass mode to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing meas urements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equ al to the leakage current specification. 6. the value of t lbotot is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by lbcr[ahd], and the number of local bus buffer delays used as programmed at powe r-on reset with configuration pins lwe[0:1] . 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at ov dd /2. 8. guaranteed by characterization. 9. guaranteed by design. figure 15 provides the ac test load for the local bus. figure 15. local bus c test load local bus clock to address valid for lad lwe[0:1] = 00 t lbklov3 ?0.8ns 3 lwe[0:1] = 11 (default) 2.3 output hold from local bus clock (except lad/ldp and lale) lwe[0:1] = 00 t lbklox1 -2.7 ? ns 3 lwe[0:1] = 11 (default) -1.8 output hold from local bus clock for lad/ldp lwe[0:1] = 00 t lbklox2 -2.7 ? ns 3 lwe[0:1] = 11 (default) -1.8 local bus clock to output high impedance (except lad/ldp and lale) lwe[0:1] = 00 t lbkloz1 ?1.0ns 5 lwe[0:1] = 11 (default) 2.4 local bus clock to output high impedance for lad/ldp lwe[0:1] = 00 t lbkloz2 ?1.0ns 5 lwe[0:1] = 11 (default) 2.4 table 31. local bus general timing parameters - dll bypassed (continued) parameter configuration 7 symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 35 local bus figure 16 to figure 21 show the local bus signals. figure 16. local bus signals, nons pecial signals only (dll enabled) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh1 t lbixkh1 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 36 freescale semiconductor local bus figure 17. local bus signals, nonspecial signals only (dll bypass mode) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkh2 t lbivkh2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 37 local bus figure 18. local bus signals, gpcm/upm si gnals for lccr[clkdiv] = 2 (dll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 38 freescale semiconductor local bus figure 19. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (dll bypass mode) internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 (dll bypass mode) lclk t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1 t lbkhkt mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 39 local bus figure 20. local bus signals, gpcm/upm signa ls for lccr[clkdiv] = 4 or 8 (dll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] t lbixkh1 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 40 freescale semiconductor local bus figure 21. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 or 8 (dll bypass mode) internal launch /capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode) lclk t lbklov1 t lbkloz1 t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1 t lbkhkt mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 41 cpm 10 cpm this section describes the dc a nd ac electrical specifications for the cpm of the mpc8541e. 10.1 cpm dc electrical characteristics table 32 provides the dc electrical characteristics for the cpm. 10.2 cpm ac timing specifications table 33 and table 34 provide the cpm input and output ac timing specifications, respectively. table 32. cpm dc electrical characteristics characteristic symbol con dition min max unit notes input high voltage v ih 2.0 3.465 v 1 input low voltage v il gnd 0.8 v 1, 2 output high voltage v oh i oh = ?8.0 ma 2.4 ? v 1 output low voltage v ol i ol = 8.0 ma ? 0.5 v 1 output high voltage v oh i oh = ?2.0 ma 2.4 ? v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 table 33. cpm input ac timing specifications 1 characteristic symbol 2 min 3 unit fcc inputs?internal clock (nmsi) input setup time t fiivkh 6ns fcc inputs?internal clock (nmsi) hold time t fiixkh 0ns fcc inputs?external clock (nmsi) input setup time t feivkh 2.5 ns fcc inputs?external clock (nmsi) hold time t feixkh b2 ns spi inputs?internal clock (nmsi) input setup time t niivkh 6ns spi inputs?internal clock (nmsi) input hold time t niixkh 0ns spi inputs?external clock (nmsi) input setup time t neivkh 4ns spi inputs?external clock (nmsi) input hold time t neixkh 2ns pio inputs?input setup time t piivkh 8ns mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 42 freescale semiconductor cpm figure 22 provides the ac test load for the cpm. figure 22. cpm ac test load figure 23 through figure 28 represent the ac timing from table 33 and table 34 . note that although the specifications generally reference th e rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. pio inputs?input hold time t piixkh 1ns col width high (fcc) t fcch 1.5 clk notes: 1. input specifications are measured from th e 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fiivkh symbolizes the fcc inputs internal timing (fi) with respect to the time the input signals (i) reaching the valid state (v) relative to the reference clock t fcc (k) going to the high (h) state or setup time. 3. pio and timer inputs and outputs are asynchronous to sysclk or any ot her externally visible clock. pio/timer inputs are internally synchronized to the cpm internal clock. pio/timer outputs should be treated as asynchronous. table 34. cpm output ac timing specifications 1 characteristic symbol 2 min max unit fcc outputs?internal clock (nmsi) delay t fikhox 15.5ns fcc outputs?external clock (nmsi) delay t fekhox 28ns spi outputs?internal clock (nmsi) delay t nikhox 0.5 10 ns spi outputs?external clock (nmsi) delay t nekhox 28ns pio outputs delay t pikhox 111ns notes: 1. output specifications are measured from the 50% level of the rising edge of clki n to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specif ications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fikhox symbolizes the fcc inputs internal timing (fi) for the time t fcc memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 33. cpm input ac timing specifications 1 (continued) characteristic symbol 2 min 3 unit output z 0 = 50 ov dd /2 r l = 50 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 43 cpm figure 23 shows the fcc internal clock. figure 23. fcc internal ac timing clock diagram figure 24 shows the fcc external clock. figure 24. fcc external ac timing clock diagram figure 25 shows ethernet collision timing on fccs. figure 25. ethernet collision ac timing diagram (fcc) fcc output signals (when gfmr tci = 1) t fikhox brg_out t fiixkh t fiivkh fcc input signals fcc output signals (when gfmr tci = 0) t fikhox fcc output signals (when gfmr tci = 1) t fekhox serial clkin t feixkh t feivkh fcc input signals fcc output signals (when gfmr tci = 0) t fekhox col (input) t fcch mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 44 freescale semiconductor cpm figure 26 shows the spi 1,2 external clock. figure 26. spi ac timing external clock diagram figure 27 shows the spi 1,2 internal clock. figure 27. spi ac timing internal clock diagram 1 spi ac timings are internal mode when it is master since spiclk is an output, and external mode when it is slave. 2 spi ac timings refe r always to spiclk . figure 28. pio signal diagram serial clkin t neixkh t neivkh t nekhox input signals: (see note) output signals: (see note) note: spi spi the clock edge is selectable on spi. brg_out t niixkh t nikhox input signals: (see note) output signals: (see note) note: t niivkh spi spi the clock edge is selectable on spi. sys clk pio inputs pio outputs t piivkh t piixkh t pikhox mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 45 cpm 10.3 cpm i2c ac specification figure 29. cpm i2c bus timing diagram the following two tables are examples of i2c ac parameters at i2c clock value of 100k and 400k respectively. table 35. i2c timing characteristic expression all frequencies unit min max scl clock frequency (slave) f scl 0f max (1) notes: 1. f max = brgclk/(min_divider*prescale. where prescaler=25-i2mode[ pdiv]; and min_divider=12 if digital filter disabled and 18 if enabled. example #1: if i2mode[pdiv]=11 (prescaler=4) and i2mode[flt]=0 (digital filter disabled) then fmax=brgclk/48 example #2: if i2mode[pdiv]=00 (prescaler=32) and i2mode[flt]=1 (digital filter enabled) then fmax=brgclk/576 hz scl clock frequency (master) f scl brgclk/16512 brgclk/48 hz bus free time between transmissions t sdhdl 1/(2.2 * f scl )-s low period of scl t sclch 1/(2.2 * f scl )-s high period of scl t schcl 1/(2.2 * f scl )-s start condition setup time 2 t schdl 2/(divider * f scl ) - (2) 2. divider = f scl /prescaler. in master mode: divider=brgclk/(f scl *prescaler)=2*(i2brg[div]+3) in slave mode : divider=brgclk/(f scl *prescaler) s start condition hold time 2 t sdlcl 3/(divider * f scl )- s data hold time 2 t scldx 2/(divider * f scl )- s data setup time 2 t sdvch 3/(divider * f scl )- s sda/scl rise time t srise - 1/(10 * f scl )s sda/scl fall time t sfall - 1/(33 * f scl )s stop condition setup time t schdh 2/(divider * f scl ) - s table 36. cpm i2c timing (f scl =100khz) characteristic expression frequency = 100khz unit min max scl clock frequency (slave) f scl 100 khz scl clock frequency (master) f scl - 100 khz bus free time between transmissions t sdhdl 4.7 - s low period of scl t sclch 4.7 - s scl sda t sdhdl t sclch t schcl t schdl t sdlcl t scldx t sdvch t srise t sfall t schdh mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 46 freescale semiconductor jtag 11 jtag this section describes the ac el ectrical specifications for the i eee 1149.1 (jtag) interface of the mpc8541e. table 38 provides the jtag ac timing specifications as defined in figure 31 through figure 34 . high period of scl t schcl 4- s start condition setup time t schdl 2- s start condition hold time t sdlcl 3- s data hold time t scldx 2- s data setup time t sdvch 3- s sda/scl rise time t srise -1 s sda/scl fall time (master) t sfall - 303 ns stop condition setup time t schdh 2- s table 37. cpm i2c timing (f scl =400khz) characteristic expression frequency = 400khz unit min max scl clock frequency (slave) f scl 400 khz scl clock frequency (master) f scl -400khz bus free time between transmissions t sdhdl 1.2 - s low period of scl t sclch 1.2 - s high period of scl t schcl 1- s start condition setup time t schdl 420 - ns start condition hold time t sdlcl 630 - ns data hold time t scldx 420 - ns data setup time t sdvch 630 - ns sda/scl rise time t srise - 250 ns sda/scl fall time t sfall -75ns stop condition setup time t schdh 420 - ns table 38. jtag ac timing speci fications (indepe ndent of sysclk) 1 at recommended operating conditions (see ta bl e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02ns trst assert time t trst 25 ? ns 3 table 36. cpm i2c timing (f scl =100khz) (continued) characteristic expression frequency = 100khz unit min max mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 47 jtag figure 30 provides the ac test load for tdo and the boundary-scan outputs of the mpc8541e. figure 30. ac test load for the jtag interface input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox ? ? ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoin t voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 30 ). time-of-flight delays must be added for trac e lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with res pect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. table 38. jtag ac timing specifications (independent of sysclk) 1 (continued) at recommended operating conditions (see ta bl e 2 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 48 freescale semiconductor jtag figure 31 provides the jtag clock input timing diagram. figure 31. jtag clock input timing diagram figure 32 provides the trst timing diagram. figure 32. trst timing diagram figure 33 provides the boundary-scan timing diagram. figure 33. boundary-scan timing diagram jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 49 i2c figure 34 provides the test access port timing diagram. figure 34. test access port timing diagram 12 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8541e. 12.1 i 2 c dc electrical characteristics table 39 provides the dc electrical characteristics for the i 2 c interface of the mpc8541e. table 39. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v input low voltage level v il ?0.3 0.3 ov dd v low level output voltage v ol 00.2 ov dd v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes whic h must be suppressed by the input filter t i2khkl 050ns3 input current each i/o pin (i nput voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a4 capacitance for each i/o pin c i ?10pf notes: 1. output voltage (open drain or open co llector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8555e powerquicc? iii integrated communications processor reference manual for information on the digital filter used. 4. i/o pins will obstruct the sda and scl lines if ov dd is switched off. vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 50 freescale semiconductor i2c 12.2 i 2 c ac electrical specifications table 40 provides the ac timing parameters for the i 2 c interface of the mpc8541e. table 40. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta b l e 3 9 ). parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 6 1.3 ? s high period of the scl clock t i2ch 6 0.6 ? s setup time for a repeated start condition t i2svkh 6 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 6 0.6 ? s data setup time t i2dvkh 6 100 ? ns data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. mpc8541e provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. 5. guaranteed by design. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 51 pci figure 15 provides the ac test load for the i 2 c. figure 35. i 2 c ac test load figure 36 shows the ac timing diagram for the i 2 c bus. figure 36. i 2 c bus ac timing diagram 13 pci this section describes the dc a nd ac electrical specifications for the pci bus of the mpc8541e. 13.1 pci dc electrical characteristics table 41 provides the dc electrical characteristic s for the pci interface of the mpc8541e. table 41. pci dc electrical characteristics 1 parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v input current i in v in 2 = 0 v or v in = v dd ?5 a high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a ?0.2v notes: 1. ranges listed do not meet the full range of the dc specifications of the pci 2.2 local bus specifications . 2. note that the symbol v in , in this case, represents the ov in symbol referenced in ta bl e 1 and ta bl e 2 . output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 52 freescale semiconductor pci 13.2 pci ac electrical specifications this section describes the general ac timing paramete rs of the pci bus of the mpc8541e. note that the sysclk signal is used as the pci input clock. table 42 provides the pci ac timing specifications at 66 mhz. note pci clock can be pci1_clk or sy sclk based on por config input. note the input setup time does not meet the pci specification. figure 15 provides the ac test load for pci. figure 37. pci ac test load table 42. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ? 6.0 ns 2, 3 output hold from clock t pckhox 2.0 ? ns 2, 9 clock to output high impedance t pckhoz ? 14 ns 2, 3, 10 input setup to clock t pcivkh 3.3 ? ns 2, 4, 9 input hold from clock t pcixkh 0 ? ns 2, 4, 9 req64 to hreset 9 setup time t pcrvrh 10 t sys ? clocks 5, 6, 10 hreset to req64 hold time t pcrhrx 050ns6, 10 hreset high to first frame assertion t pcrhfv 10 ? clocks 7, 10 notes: 1. note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. 5. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the mini mum and maximum defined ra nges. for values see section 15, ?clocking .? 6. the setup and hold time is with respect to the rising edge of hreset . 7. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications . 8. the reset assertion timi ng requirement for hreset is 100 s. 9. guaranteed by characterization. 10.guaranteed by design. output z 0 = 50 ov dd /2 r l = 50 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 53 package and pin listings figure 38 shows the pci input ac timing conditions. figure 38. pci input ac timing measurement conditions figure 39 shows the pci output ac timing conditions. figure 39. pci output ac timing measurement condition 14 package and pin listings this section details package paramete rs, pin assignments, and dimensions. 14.1 package parameters for the mpc8541e fc-pbga the package parameters are as provided in th e following list. the package type is 29 mm 29 mm, 783 flip chip plastic ball grid array (fc-pbga). die size 8.7 mm 9.3 mm 0.75 mm package outline 29 mm 29 mm interconnects 783 pitch 1 mm minimum module height 3.07 mm maximum module height 3.75 mm solder balls 62 sn/36 pb/2 ag ball diameter (typical) 0.5 mm t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 54 freescale semiconductor package and pin listings 14.2 mechanical dimensions of the fc-pbga figure 40 the mechanical dimensions and bottom surface nomenclature of the mpc8541e 783 fc-pbga package. figure 40. mechanical dimensions and bottom surface nomenclature of the fc-pbga notes 1. all dimensions are in millimeters . 2. dimensions and tolera nces per asme y14.5m-1994. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 55 package and pin listings 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. the socket lid must alwa ys be oriented to a1. 14.3 pinout listings table 43 provides the pin-out listing fo r the mpc8541e, 783 fc-pbga package. table 43. mpc8541e pinout listing signal package pin number pin type power supply notes pci1 and pci2 (one 64-bit or two 32-bit) pci1_ad[63:32], pci2_ad[31:0] aa14, ab14, ac14, ad14, ae14, af14, ag14, ah14, v15, w15, y15, aa15, ab15, ac15, ad15, ag15, ah15, v16, w16, ab16, ac16, ad16, ae16, af16, v17, w17, y17, aa17, ab17, ae17, af17, af18 i/o ov dd 17 pci1_ad[31:0] ah6, ad7, ae7, ah7, ab8, ac8, af8, ag8, ad9, ae9, af9, ag9, ah9, w10, y10, aa10, ae11, af11, ag11, ah11, v12, w12, y12, ab12, ad12, ae12, ag12, ah12, v13, y13, ab13, ac13 i/o ov dd 17 pci_c_be64 [7:4] pci2_c_be [3:0] ag13, ah13, v14, w14 i/o ov dd 17 pci_c_be64 [3:0] pci1_c_be [3:0] ah8, ab10, ad11, ac12 i/o ov dd 17 pci1_par aa11 i/o ov dd pci1_par64/pci2_par y14 i/o ov dd pci1_frame ac10 i/o ov dd 2 pci1_trdy ag10 i/o ov dd 2 pci1_irdy ad10 i/o ov dd 2 pci1_stop v11 i/o ov dd 2 pci1_devsel ah10 i/o ov dd 2 pci1_idsel aa9 i ov dd pci1_req64 /pci2_frame ae13 i/o ov dd 5, 10 pci1_ack64 /pci2_devsel ad13 i/o ov dd 2 pci1_perr w11 i/o ov dd 2 pci1_serr y11 i/o ov dd 2, 4 pci1_req[ 0] af5 i/o ov dd pci1_req [1:4] af3, ae4, ag4, ae5 i ov dd mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 56 freescale semiconductor package and pin listings pci1_gnt [0] ae6 i/o ov dd pci1_gnt [1:4] ag5, ah5, af6, ag6 o ov dd 5, 9 pci1_clk ah25 i ov dd pci2_clk ah27 i ov dd pci2_gnt [0] ac18 i/o ov dd pci2_gnt [1:4] ad18, ae18, ae19, ad19 o ov dd 5, 9 pci2_idsel ac22 i ov dd pci2_irdy ad20 i/o ov dd 2 pci2_perr ac20 i/o ov dd 2 pci2_req [0] ad21 i/o ov dd pci2_req [1:4] ae21, ad22, ae22, ac23 i ov dd pci2_serr ae20 i/o ov dd 2,4 pci2_stop ac21 i/o ov dd 2 pci2_trdy ac19 i/o ov dd 2 ddr sdram memory interface mdq[0:63] m26, l27, l22, k24, m24, m23, k27, k26, k22, j28, f26, e27, j26, j23, h26, g26, c26, e25, c24, e23, d26, c25, a24, d23, b23, f22, j21, g21, g22, d22, h21, e21, n18, j18, d18, l17, m18, l18, c18, a18, k17, k16, c16, b16, g17, l16, a16, l15, g15, e15, c14, k13, c15, d15, e14, d14, d13, e13, d12, a11, f13, h13, a13, b12 i/o gv dd mecc[0:7] n20, m20, l19, e19, c21, a21, g19, a19 i/o gv dd mdm[0:8] l24, h28, f24, l21, e18, e16, g14, b13, m19 o gv dd mdqs[0:8] l26, j25, d2 5, a22, h18, f16, f14, c13, c20 i/o gv dd mba[0:1] b18, b19 o gv dd ma[0:14] n19, b21, f21, k21, m 21, c23, a23, b24, h23, g24, k19, b25, d27, j14, j13 ogv dd mwe d17 o gv dd mras f17 o gv dd mcas j16 o gv dd mcs [0:3] h16, g16, j15, h15 o gv dd mcke[0:1] e26, e28 o gv dd 11 mck[0:5] j20, h25, a15, d20, f28, k14 o gv dd mck [0:5] f20, g27, b15, e20, f27, l14 o gv dd table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 57 package and pin listings msync_in m28 i gv dd 22 msync_out n28 o gv dd 22 local bus controller interface la[27] u18 o ov dd 5, 9 la[28:31] t18, t19, t20, t21 o ov dd 5, 7, 9 lad[0:31] ad26, ad27, ad28, ac26, ac27, ac28, aa22, aa23, aa26, y21, y22, y26, w20, w22, w26, v19, t22, r24, r23, r22, r21, r18, p26, p25, p20, p19, p18, n22, n23, n24, n25, n26 i/o ov dd lale v21 o ov dd 5, 8, 9 lbctl v20 o ov dd 9 lcke u23 o ov dd lclk[0:2] u27, u28, v18 o ov dd lcs [0:4] y27, y28, w27, w28, r27 o ov dd lcs5 /dma_dreq2 r28 i/o ov dd 1 lcs6 /dma_dack2 p27 o ov dd 1 lcs7 /dma_ddone2 p28 o ov dd 1 ldp[0:3] aa27, aa28, t26, p21 i/o ov dd lgpl0/lsda10 u19 o ov dd 5, 9 lgpl1/lsdwe u22 o ov dd 5, 9 lgpl2/loe /lsdras v28 o ov dd 5, 8, 9 lgpl3/lsdcas v27 o ov dd 5, 9 lgpl4/lgta /lupwait/ lpbse v23 i/o ov dd 21 lgpl5 v22 o ov dd 5, 9 lsync_in t27 i ov dd lsync_out t28 o ov dd lwe [0:1]/lsddqm[0:1]/ lbs [0:1] ab28, ab27 o ov dd 1, 5, 9 lwe [2:3]/lsddqm[2:3]/ lbs [2:3] t23, p24 o ov dd 1, 5, 9 dma dma_dreq [0:1] h5, g4 i ov dd dma_dack [0:1] h6, g5 o ov dd table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 58 freescale semiconductor package and pin listings dma_ddone [0:1] h7, g6 o ov dd programmable interrupt controller mcp ag17 i ov dd ude ag16 i ov dd irq[0:7] aa18, y18, ab18, ag24, aa21, y19, aa19, ag25 i ov dd irq8 ab20 i ov dd 9 irq9/dma_dreq3 y20 i ov dd 1 irq10/dma_dack3 af26 i/o ov dd 1 irq11/dma_ddone3 ah24 i/o ov dd 1 irq_out ab21 o ov dd 2, 4 ethernet management interface ec_mdc f1 o ov dd 5, 9 ec_mdio e1 i/o ov dd gigabit reference clock ec_gtx_clk125 e2 i lv dd three-speed ethernet contro ller (gigabit ethernet 1) tsec1_txd[7:4] a6, f7, d7, c7 o lv dd tsec1_txd[3:0] b7, a7, g8, e8 o lv dd 9, 18 tsec1_tx_en c8 o lv dd 11 tsec1_tx_er b8 o lv dd tsec1_tx_clk c6 i lv dd tsec1_gtx_clk b6 o lv dd tsec1_crs c3 i lv dd tsec1_col g7 i lv dd tsec1_rxd[7:0] d4, b4, d3 , d5, b5, a5, f6, e6 i lv dd tsec1_rx_dv d2 i lv dd tsec1_rx_er e5 i lv dd tsec1_rx_clk d6 i lv dd three-speed ethernet contro ller (gigabit ethernet 2) tsec2_txd[7:4] b10, a10, j10, k11 o lv dd tsec2_txd[3:0] j11, h11, g11, e11 o lv dd 5, 9, 18 table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 59 package and pin listings tsec2_tx_en b11 o lv dd 11 tsec2_tx_er d11 o lv dd tsec2_tx_clk d10 i lv dd tsec2_gtx_clk c10 o lv dd tsec2_crs d9 i lv dd tsec2_col f8 i lv dd tsec2_rxd[7:0] f9, e9, c9, b9, a9, h9, g10, f10 i lv dd tsec2_rx_dv h8 i lv dd tsec2_rx_er a8 i lv dd tsec2_rx_clk e10 i lv dd duart uart_cts [0,1] y2, y3 i ov dd uart_rts [0,1] y1, ad1 o ov dd uart_sin[0,1] p11, ad5 i ov dd uart_sout[0,1] n6, ad2 o ov dd i 2 c interface iic_sda ah22 i/o ov dd 4, 19 iic_scl ah23 i/o ov dd 4, 19 system control hreset ah16 i ov dd hreset_req ag20 o ov dd 18 sreset af20 i ov dd ckstp_in m11 i ov dd ckstp_out g1 o ov dd 2, 4 debug trig_in n12 i ov dd trig_out/ready g2 o ov dd 6, 9, 18 msrcid[0:1] j9, g3 o ov dd 5, 6, 9 msrcid[2:3] f3, f5 o ov dd 6 msrcid4 f2 o ov dd 6 mdval f4 o ov dd 6 table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 60 freescale semiconductor package and pin listings clock sysclk ah21 i ov dd rtc ab23 i ov dd clk_out af22 o ov dd jtag tck af21 i ov dd tdi ag21 i ov dd 12 tdo af19 o ov dd 11 tms af23 i ov dd 12 trst ag23 i ov dd 12 dft lssd_mode ag19 i ov dd 20 l1_tstclk ab22 i ov dd 20 l2_tstclk ag22 i ov dd 20 test_sel0 ah20 i ov dd 3 test_sel1 ag26 i ov dd 3 thermal management therm0 ag2 ? ? 14 therm1 ah3 ? ? 14 power management asleep ag18 9, 18 power and ground signals av dd 1 ah19 power for e500 pll (1.2 v) av dd 1 av dd 2ah18 power for ccb pll (1.2 v) av dd 2 av dd 3 ah17 power for cpm pll (1.2 v) av dd 3 av dd 4af28 power for pci1 pll (1.2 v) av dd 4 av dd 5 ae28 power for pci2 pll (1.2 v) av dd 5 table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 61 package and pin listings gnd a12, a17, b3, b14, b20, b26, b27, c2, c4, c11,c17, c19, c22, c27, d8, e3, e12, e24, f11, f18, f23, g9, g12, g25, h4, h12, h14, h 17, h20, h22, h27, j19, j24, k5, k9, k18, k23, k28, l6, l20, l25, m4, m12, m14, m16, m22, m27, n2, n1 3, n15, n17, p12, p14, p16, p23, r13, r15, r17, r20, r26, t3, t8, t10, t12, t14, t16, u6, u13, u15, u16, u17, u21, v7, v10, v26, w5, w18, w23, y8, y16, aa6, aa13, ab4, ab11, ab19, ac6, ac9, ad3, ad8, ad17, af2, af4, af10, af13, af15, af27, ag3, ag7 ?? gv dd a14, a20, a25, a26, a27, a28, b17, b22, b28, c12, c28, d16, d19, d21, d24, d28, e17, e22, f12, f15, f19, f25, g13, g18, g20, g23, g28, h19, h24, j12, j17, j22, j27, k15, k20, k25, l13, l23, l28, m25, n21 power for ddr dram i/o voltage (2.5 v) gv dd lv dd a4, c5, e7, h10 reference voltage; three-speed ethernet i/o (2.5 v, 3.3 v) lv dd mv ref n27 reference voltage signal; ddr mv ref no connects aa24, aa25, aa3 , aa4, aa7 aa8, ab24, ab25, ac24, ac25, ad23, ad24, ad25, ae23, ae24, ae25, ae26, ae27, af24, af 25, h1, h2, j1, j2, j3, j4, j5, j6, m1, n1, n10, n11, n4, n5, n7, n8, n9, p10, p8, p9, r10, r11, t24, t25, u24, u25, v24, v25, w24, w25, w9, y24, y25, y5, y6, y9, ah26, ah28, ag28, ah1, ag1, ah2, b1, b2, a2, a3 ??16 ov dd d1, e4, h3, k4, k10, l7, m5, n3, p22, r19, r25, t2, t7, u5, u20, u26, v8, w4, w13, w19, w21, y7, y23, aa5, aa12, aa16, aa20, ab7, ab9, ab26, ac5, ac11, ac17, ad4, ae1, ae8, ae10, ae1 5, af7, af12, ag27, ah4 pci, 10/100 ethernet, and other standard (3.3 v) ov dd reserved c1, t11, u11, af1 ? ? 15 sensevdd l12 power for core (1.2 v) v dd 13 sensevss k12 ? ? 13 v dd m13, m15, m17, n14, n16, p13, p15, p17, r12, r14, r16, t13, t15, t17, u12, u14 power for core (1.2 v) v dd cpm pa[8:31] j7, j8, k8, k7, k6, k3, k2, k1, l1, l2, l3, l4, l5, l8, l9, l10, l11, m10, m9, m8, m7, m6, m3, m2 i/0 ov dd table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 62 freescale semiconductor package and pin listings pb[18:31] p7, p6, p5, p4, p3, p2 , p1, r1, r2, r3, r4, r5, r6, r7 i/0 ov dd pc[0, 1, 4-29] r8, r9, t9, t6, t5, t4, t1, u1, u2, u3, u4, u7, u8, u9, u10, v9, v6, v5, v4, v3, v2, v1, w1, w2, w3, w6, w7, w8 i/0 ov dd pd[7, 14-25, 29-31] y4, aa2, aa1, ab1, ab2, ab3, ab5, ab6, ac7, ac4, ac3, ac2, ac1, ad6, ae3, ae2 i/0 ov dd notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller interface section, and is not mentioned in the dma sectio n even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 3. this pin must always be pulled down to gnd. 4. this pin is an open drain signal. 5. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the mpc8541e is in the reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. if an external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intend ed to be high during reset. 6. treat these pins as no connects (nc) unless using debug address functionality. 7. the value of la[28:31] during re set sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 15.2, ?platform/system pll ratio .? 8. the value of lale and lgpl2 at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the section 15.3, ?e500 core pll ratio .? 9. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for boundary scan. 10.this pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit pci operation. therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-b it pci device. refer to the pci specification . 11.this output is actively driven during rese t rather than being three-stated during reset. 12.these jtag pins have weak internal pull-up p-fets that are always enabled. 13.these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14.internal thermally sensitive resistor. 15.no connections should be made to these pins. 16.these pins are not connected for any functional use. 17.pci specifications recommend that a weak pull-up resistor (2?10 k ) be placed on the higher order pins to ov dd when using 64-bit buffer mode (pins pci_ad[63:32] and pci2_c_be [7:4]). 18. if this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to pull this signal to a logic 1 during reset. 19. recommend a pull-up resistor (~1 k ) be placed on this pin to ov dd . 20. these are test signals for factor y use only and must be pulled up (100 ? 1 k ) to ov dd for normal machine operation. 21. if this signal is used as both an input and an output, a weak pull-up (~ 10 k ) is required on this pin. 22. msync_in and msync_out should be c onnected together for proper operation. table 43. mpc8541e pinout listing (continued) signal package pin number pin type power supply notes mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 63 clocking 15 clocking this section describes the pll confi guration of the mpc8541e. note that the platform clock is identical to the ccb clock. 15.1 clock ranges table 44 provides the clocking specificati ons for the processor core and table 45 provides the clocking specifications for the memory bus. table 44. processor core clocking specifications characteristic maximum processor core frequency unit notes 533 mhz 600 mhz 667 mhz 833 mhz 1000 mhz min max min max min max min max min max e500 core processor frequency 400 533 400 600 400 667 400 833 400 1000 mhz 1, 2, 3 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 15.2, ?platform/system pll ratio ,? and section 15.3, ?e500 core pll ratio ,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 200 mhz. 3. 1000 mhz frequency supports only a 1.3 v core. table 45. memory bus clocking specifications characteristic maximum processor core frequency unit notes 533, 600, 667, 883, 1000 mhz min max memory bus frequency 100 166 mhz 1, 2, 3 notes: 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 15.2, ?platform/system pll ratio ,? and section 15.3, ?e500 core pll ratio ,? for ratio settings. 2. the memory bus speed is half of the ddr data ra te, hence, half of the platform clock frequency. 3. 1000 mhz frequency supports only a 1.3 v core. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 64 freescale semiconductor clocking 15.2 platform/system pll ratio the platform clock is the clock that drives the l2 cache, the dd r sdram data rate, and the e500 core complex bus (ccb), and is also ca lled the ccb clock. the values are determined by the binary value on la[28:31] at power up, as shown in table 46 . there is no default for this pll ratio; these signals must be pulled to the desired values. for specifications on the pci_clk, refer to the pci 2.2 specification. table 46. ccb clock ratio binary value of la[28:31] signals ratio description 0000 16:1 ratio ccb cl ock: sysclk (pci bus) 0001 reserved 0010 2:1 ratio ccb clock: sysclk (pci bus) 0011 3:1 ratio ccb clock: sysclk (pci bus) 0100 4:1 ratio ccb clock: sysclk (pci bus) 0101 5:1 ratio ccb clock: sysclk (pci bus) 0110 6:1 ratio ccb clock: sysclk (pci bus) 0111 reserved 1000 8:1 ratio ccb clock: sysclk (pci bus) 1001 9:1 ratio ccb clock: sysclk (pci bus) 1010 10:1 ratio ccb cl ock: sysclk (pci bus) 1011 reserved 1100 12:1 ratio ccb cl ock: sysclk (pci bus) 1101 reserved 1110 reserved 1111 reserved mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 65 clocking 15.3 e500 core pll ratio table 47 describes the clock ratio between the e500 core complex bus (ccb) and the e500 core clock. this ratio is determined by the binary value of lale and lgpl2 at power up, as shown in table 47 . 15.4 frequency options table 48 shows the expected fr equency values for the platform fre quency when using a ccb to sysclk ratio in comparison to the memory bus speed. table 47. e500 core to ccb ratio binary value of lale, lgpl2 signals ratio description 00 2:1 e500 core:ccb 01 5:2 e500 core:ccb 10 3:1 e500 core:ccb 11 7:2 e500 core:ccb table 48. frequency options with respect to memory bus speeds ccb to sysclk ratio sysclk (mhz) 17 25 33 42 67 83 100 111 133 platform/ccb frequency (mhz) 2 200 222 267 3 200 250 300 333 4 267 333 5 208 333 6 200 250 8 200 267 333 9 225 300 10 250 333 12 200 300 16 267 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 66 freescale semiconductor thermal 16 thermal this section describes the therma l specifications of the mpc8541e. 16.1 thermal characteristics table 49 provides the package thermal ch aracteristics for the mpc8541e. 16.2 thermal management information this section provides thermal management information fo r the flip chip plastic ba ll grid array (fc-pbga) package for air-cooled applications. proper ther mal control design is primarily dependent on the system-level design?the heat sink, airflow, and thermal interfac e material. the recommended attachment method to the heat sink is illustrated in figure 41 . the heat sink should be att ached to the printed-circuit board with the spring force centered over the die. this spring force should not exceed 10 pounds force. table 49. package thermal characteristics characteristic symbol value unit notes junction-to-ambient natural convection on four layer board (2s2p) r jma 17 c/w 1, 2 junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p) r jma 14 c/w 1, 2 junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p) r jma 13 ?c/w 1, 2 junction-to-board thermal r jb 10 ?c/w 3 junction-to-case thermal r jc 0.96 ?c/w 4 notes 1. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on th e board, and board thermal resistance 2. per jedec jesd51-6 with the board horizontal. 3. thermal resistance between the die and the printed-circui t board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. 4. thermal resistance between the die and the case top surfac e as measured by the cold plate method (mil spec-883 method 1012.1). cold plate temperatur e is used for case temperature; measured value includes the thermal resistance of the interface layer. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 67 thermal figure 41. package exploded cross-sectional view with several heat sink options the system board designer can choose between severa l types of heat sinks to place on the mpc8541e. there are several commerci ally-available heat sinks from the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aav idthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alp hanovatech.com international electron ic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-millennium.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com heat sink fc-pbga package heat sink clip printed-circuit board die lid thermal interface material mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 68 freescale semiconductor thermal ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment me thod, assembly, a nd cost. several heat sinks offered by aavid therma lloy, alpha novatech, ierc, chip coolers, millennium electronics, and wakefield engineering offer diff erent heat sink-to-ambient thermal resistances, that will allow the mpc8541e to function in various environments. 16.2.1 recommended thermal model for system thermal modeling, the mp c8541e thermal model is shown in figure 42 . five cuboids are used to represent this device. to simplif y the model, the solder balls and s ubstrate are modeled as a single block 29x29x1.6 mm with the conducti vity adjusted accordingly. the di e is modeled as 8.7 x 9.3 mm at a thickness of 0.75 mm. the bump/ underfill layer is modeled as a collap sed resistance between the die and substrate assuming a conductivity of 4.4 w/m?k in the thickness dimension of 0.07 mm. the lid attach adhesive is also modeled as a collapsed resist ance with dimensions of 8.7 x 9.3 x 0.05 mm and the conductivity of 1.07 w/m?k. the nickel plated copper lid is modeled as 11 x 11 x 1 mm. figure 42. mpc8541e thermal model die lid substrate and solder balls heat source substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit lid (11 11 1 mm) k x 360 w/(m k) k y 360 k z 360 lid adhesive?colla psed resistance (8.7 9.3 0.05 mm) k z 1.07 die (8.7 9.3 0.75 mm) bump/underfill?collapsed resistance (8.7 9.3 0.07 mm) k z 4.4 substrate and solder balls (25 25 1.6 mm) k x 14.2 k y 14.2 k z 1.2 adhesive bump/underfill mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 69 thermal 16.2.2 internal package conduction resistance for the packaging technology, shown in table 49 , the intrinsic internal conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-board thermal resistance figure 43 depicts the primary heat transfer path for a p ackage with an attached heat sink mounted to a printed-circuit board. figure 43. package with heat sink mounted to a printed-circuit board the heat sink removes most of the he at from the device. heat generated on the active side of the chip is conducted through the silicon and through the lid, then th rough the heat sink attach material (or thermal interface material), and fi nally to the heat sink. the junction-to-case thermal re sistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 16.2.3 thermal interface materials a thermal interface material is required at the pa ckage-to-heat sink interface to minimize the thermal contact resistance. for those applic ations where the heat sink is at tached by spring clip mechanism, figure 44 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resist ance. the bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. heat sinks are attached to the package by means of a sp ring clip to holes in the printed-circu it board (see figure 40 ). therefore, the synthetic grease offers the be st thermal performance, especially at the low interface pressure. when removing the heat sink for re-work, it is preferable to slide th e heat sink off slowly until the thermal interface material loses its grip. if the support fixture around the package prevents sliding off the heat sink, external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance) mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 70 freescale semiconductor thermal the heat sink should be slowly rem oved. heating the heat sink to 40-50 ? c with an air gun can soften the interface material and make the removal easier. the use of an adhesive for heat sink attach is not recommended. figure 44. thermal performance of select thermal interface materials the system board designer can choose between severa l types of thermal interface. there are several commercially-available thermal interf aces provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78 th st. 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w) mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 71 thermal chanhassen, mn 55317 internet: www.bergquistcompany.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 16.2.4 heat sink selection examples the following section pr ovides a heat sink se lection example using one of th e commercially available heat sinks. 16.2.4.1 case 1 for preliminary heat sink sizing, the die-juncti on temperature can be expressed as follows: t j = t i + t r + ( jc + int + sa ) p d where t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device. see table 4 and table 5 . during operation the die-junction temperatures (t j ) should be maintained within the range specified in table 2 . the temperature of air cooling the component greatly depends on th e ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electr onic cabinet inlet- air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of some thermal interface material ( int ) may be about 1 c/w. for the purposes of this example, the jc value given in table 49 that includes the thermal grease interface and is documented in note 4 is used. if a thermal pad is used, int must be added. assuming a t i of 30 c, a t r of 5 c, a fc-pbga package jc = 0.96, and a power consumption (p d ) of 8.0 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.96 c/w + sa ) 8.0 w the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity for a thermalloy heat sink #2328b is shown in figure 45 . assuming an air velocity of 2 m/s, we have an effective sa+ of about 3.3 c/w, thus t j = 30 c + 5 c + (0.96 c/w + 3.3 c/w) 8.0 w, resulting in a die-junction temperature of approxi mately 69 c which is well within the maximum operating temperature of the component. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 72 freescale semiconductor thermal figure 45. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity 16.2.4.2 case 2 every system application has differen t conditions that the thermal manage ment solution must solve. as an alternate example, assume that the air reaching the co mponent is 85 c with an approach velocity of 1 m/sec. for a maximum junction temper ature of 105 c at 8 w, the total thermal resi stance of junction to case thermal resistance plus therma l interface material plus heat sink thermal resistan ce must be less than 2.5 c/w. the value of the junction to case thermal resistance in table 49 includes the thermal interface resistance of a thin layer of therma l grease as documented in footnote 4 of the table. assuming that the heat sink is flat enough to allow a thin layer of grease or phase change ma terial, then the heat sink must be less than 1.5 c/w. millennium electronics (mei) ha s tooled a heat sink mtherm-1051 for this requirement assuming a compactpci environment at 1 m/sec and a heat sink height of 12 mm . the mei solution is illustrated in figure 46 and figure 47 . this design has several significant advantages: ? the heat sink is clipped to a plastic frame attached to the appl ication board with screws or plastic inserts at the corners away from the primary signal routing areas. ? the heat sink clip is designed to apply the forc e holding the heat sink in place directly above the die at a maximum force of less than 10 lbs. ? for applications with significant vibration requirements, silicone damping mate rial can be applied between the heat sink and plastic frame. 1 3 5 7 8 00.511.522.533.5 thermalloy #2328b pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance ( c/w) (25 28 15 mm) 2 4 6 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 73 thermal the spring mounting should be designed to apply the fo rce only directly above the die. by localizing the force, rocking of the heat sink is minimized. one suggested mounting me thod attaches a plastic fence to the board to provide the structure on which the heat sink spring clips. th e plastic fence also provides the opportunity to minimize the holes in the printed-circui t board and to locate them at the corners of the package. figure 46 and provide exploded views of the plas tic fence, heat sink, and spring clip. figure 46. exploded views (1) of a heat sink attachment using a plastic fence mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 74 freescale semiconductor thermal figure 47. exploded views (2) of a heat sink attachment using a plastic force the die junction-to-ambient and the heat sink-to-ambient thermal resi stances are common figure-of-merits used for comparing the thermal performance of va rious microelectronic pa ckaging technologies, one should exercise caution when only us ing this metric in determining th ermal management because no single parameter can adequately descri be three-dimensional heat flow . the final die-junction operating temperature is not only a function of the component-le vel thermal resistance, but the system level design and its operating conditions. in addition to the compone nt?s power consumption, a number of factors affect the final operating die-junc tion temperature: airflow, board populat ion (local heat fl ux of adjacent components), system air temp erature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s microelectronic equipment, the comb ined effects of the heat transfer mechanisms (radi ation convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 75 system design information 17 system design information this section provides elect rical and thermal design r ecommendations for successf ul application of the mpc8541e. 17.1 system clocking the mpc8541e includes five plls. 1. the platform pll (av dd 1 ) generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is se lected using the platform pll ratio configuration bits as described in section 15.2, ?platform/system pll ratio .? 2. the e500 core pll (av dd 2 ) generates the core clock as a slave to the platform clock. the frequency ratio between the e500 core clock and the platform cl ock is selected using the e500 pll ratio configuration bits as described in section 15.3, ?e500 core pll ratio .? 3. the cpm pll (av dd 3) is slaved to the platform clock a nd is used to generate clocks used internally by the cpm block. the ratio between the cpm pll and th e platform clock is fixed and not under user control. 4. the pci1 pll (av dd 4) generates the clocking for the first pci bus. 5. the pci2 pll (av dd 5) generates the clock for the second pci bus. 17.2 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd 1, av dd 2, av dd 3, av dd 4, and av dd 5 respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to relia bly provide power to the plls, but the recommended solution is to provide five independe nt filter circuits as illustrated in figure 48 , one to each of the five av dd pins. by providing independent filters to eac h pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommenda tions of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route direct ly from the capacitors to the av dd pin, which is on the periphery of the 783 fc-pbg a footprint, without the inductance of vias. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 76 freescale semiconductor system design information figure 48 shows the pll power supply filter circuit. figure 48. pll power supply filter circuit 17.3 decoupling recommendations due to large address and da ta buses, and high operati ng frequencies, the mpc8541e can generate transient power surges and high freque ncy noise in its power suppl y, especially while drivi ng large capacitive loads. this noise must be prevented from reaching ot her components in the mpc8541e system, and the mpc8541e itself requires a clean, tight ly regulated source of power. ther efore, it is recommended that the system designer place at least one decoupli ng capacitor at each v dd , ov dd , gv dd , and lv dd pins of the mpc8541e. these decoupling capacitors s hould receive their power from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, util izing short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a va lue of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be severa l bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors shoul d have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connect ed to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 17.4 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc ( no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the mpc8541e. 17.5 output buffer dc impedance the mpc8541e drivers are characterize d over process, voltage, and temper ature. for all buses, the driver is a push-pull single-ended driv er type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external re sistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until th e pad voltage is ov dd /2 (see figure 49 ). the output impedance is the av erage of two components, the resistances of the pul l-up and pull-down devices. v dd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors 10 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 77 system design information when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistan ce of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 49. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the out put voltage is measured while driving l ogic 1 without an exte rnal differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precisi on differential termination resistor of value r term . the measured voltage is v 2 = 1/(1/r 1 +1/r 2 )) i source . solving for the outpu t impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . table 50 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. table 50. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 43 target 25 target 20 target z 0 r p 43 target 25 target 20 target z 0 differential na na na z diff note: nominal supply voltages. see ta b l e 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2 mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 78 freescale semiconductor system design information 17.6 configuration pin multiplexing the mpc8541e provides the user with power-on confi guration options which can be set through the use of external pull-up or pul l-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generall y used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time th e input receiver is disabled and the i/o circuit takes on its nor mal function. most of these sample d configuration pins are equipped with an on-chip gated resist or of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resist or is enabled only during hreset (and for platform/system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowi ng functional operation of the pin as an output with minimal signal quality or delay disrup tion. the default value for all confi guration bits treated this way has been encoded such that a high volta ge level puts the device into the defa ult state and extern al resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to th ese pull-down resistors coupl ed with the large value of the pull-down resistor should mini mize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e500 p ll ratio configuration pi ns are not equipped with these default pull-up devices. 17.7 pull-up resistor requirements the mpc8541e requires high resist ance pull-up resistors (10 k is recommended) on open drain type pins. correct operation of the jtag interface requires conf iguration of a group of system control pins as demonstrated in figure 51 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavi or and spurious assertion will give unpredictable results. tsec1_txd[3:0] must not be pulle d low during reset. some phy chip s have internal pulldowns that could cause this to happen. if such ph y chips are used, then a pullup must be placed on these signals strong enough to restore these signals to a logical 1 during reset. refer to the pci 2.2 specification for all pull-ups required for pci. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 79 system design information 17.8 jtag configuration signals boundary-scan testing is enabled thro ugh the jtag interface signals. the trst signal is optional in the ieee std 1149.1 specification, but is provided on all processors that implement the power architecture. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operati on. while it is possible to force the tap controller to the reset state using only the tck and tms signals, ge nerally systems wi ll assert trst during the power-on reset flow. simply tying trst to hreset is not practical because the jtag in terface is also used for accessing the common on-chip proce ssor (cop) function. the cop function of these processors allow a remote computer system (typically, a pc with dedicated hardware and debugging softwa re) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures , or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 50 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 50 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefi ts such as breakpoints, watc hpoints, register and memory examination/modification, and other standard debugger features. an in expensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop header; consequently , many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numberi ng, the signal placement recommended in figure 50 is common to all known emulators. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 80 freescale semiconductor system design information figure 50. cop connector physical pinout 17.8.1 termination of unused signals if the jtag interface and cop head er will not be used, freescale reco mmends the following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 51 . if this is not pos sible, the isolation resistor w ill allow future access to trst in case a jtag interface may need to be wire d onto the system in future debug situations. ? tie tck to ov dd through a 10 k resistor. this will preven t tck from changing state and reading incorrect data into the device. ? no connection is required for tdi, tms, or tdo. 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi nc nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 81 system design information figure 51. jtag interface connection hreset from target board sources cop_hreset 13 cop_sreset sreset nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 notes: 3. the key location (pin 14) is not physically present on the cop header. 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc sreset 2. populate this with a 10 resistor for short-circuit/current-limiting protection. nc ov dd 10 k 10 k hreset 1 in order to fully control the processor as shown here. 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for 1. the cop port and target board should be able to independently assert hreset and trst to the processor improved signal integrity. tck 4 5 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. 10 k 6 6. asserting sreset causes a machine check interrupt to the e500 core. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 82 freescale semiconductor document revision history 18 document revision history table 51 provides a revision history fo r this hardware specification. 19 device nomenclature ordering information for the part s fully covered by this specifi cation document is provided in section 19.1, ?nomenclature of parts fu lly addressed by this document.? table 51. document revision history rev. no. date substantive change(s) 4 updated section 2.1.2, ?power sequencing.? updated back page information. 3.2 11/2006 updated section 2.1.2, ?power sequencing.? replaced section 17.8, ?jtag co nfiguration signals.? 3.1 10/2005 ta b l e 4 : added footnote 2 about junction temperature. ta b l e 4 : added max. power values for 1000 mhz core frequency. removed figure 6 , ?maximum ac waveforms on pci interface for 3.3-v signaling.? ta b l e 3 0 : modified note to t lbkskew f rom 8 to 9 ta b l e 3 0 : changed t lbkhoz1 and t lbkhov2 values. ta b l e 3 0 : added note 3 to t lbkhov1 . ta b l e 3 0 and ta bl e 3 1 : modified note 3. ta b l e 3 1 : added note 3 to t lbklov1 . ta b l e 3 1 : modified values for t lbkhkt , t lbklov1 , t lbklov2 , t lbklov3 , t lbkloz1 , and t lbkloz2 . figure 20 : changed input signals: lad[0:31]/ldp[0:3]. ta b l e 4 3 : modified note for signal clk_out. ta b l e 4 3 : pci1_clk and pci2_clk changed from i/o to i. ta b l e 5 2 : added column for en cryption acceleration. 3 8/29/2005 ta b l e 4 : modified max. power values. ta b l e 4 3 : modified notes for signals tsec1_txd[ 3:0], tsec2_txd[3:0], trig_out/ready, msrcid4, and mdval. 2 8/2005 previous revision?s history lis ted incorrect cross references. table 2 is now correctly listed as ta b l e 2 7 and table 31 is now listed as ta b l e 3 1 . ta b l e 7 : added note 2. ta b l e 1 4 : modified min and max values for t ddkhmp 1 6/2005 ta b l e 2 7 : changed lv dd to ov dd for the supply voltage ethernet management interface. ta b l e 4 : modified footnote 4 and changed typical power for the 1000mhz core frequency. ta b l e 3 1 : corrected symbols for body rows 9?15, effectivel y changing them from a high state to a low state. 0 6/2005 initial release. mpc8541e powerquicc? iii integrated communicat ions processor hardware specifications, rev. 4 freescale semiconductor 83 device nomenclature 19.1 nomenclature of parts fully addressed by this document table 52 provides the freescale part num bering nomenclature for the mpc 8541e. note that the individual part numbers correspond to a maximum processor core frequency. for av ailable frequencies, contact your local freescale sales office. in a ddition to the processor frequency, the part numbering scheme also includes an application modifier wh ich may specify special application conditions. each part number also contains a revision code which refe rs to the die mask revision number. 19.2 part marking parts are marked as the example shown in figure 52 . figure 52. part marking for fc-pbga device table 52. part numbering nomenclature mpc nnnn t pp aa a r product code part identifier encryption acceleration temperature range 1 package 2 processor frequency 3 platform frequency revision level 4 mpc 8541 blank = not included e = included blank = 0 to 105 c c = ?40 to 105 c px = fc-pbga vt = fc-pbga (lead free) aj = 533 mhz ak = 600 mhz al = 667 mhz ap = 833 mhz aq = 1000 mhz d = 266 mhz e = 300 mhz f = 333 mhz notes: 1. for temperature range=c, processor frequency is limited to 667 mhz with a platform frequency selector of 333 mhz, processor frequency is limited to 533 mhz with a platform frequency selector of 266 mhz. 2. see section 14, ?package and pin listings ,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. 4. contact you local freescale field applications engineer (fae). mpc85nn xpxxxxn mmmmm atwlyywwa notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmm is the 5-digit mask number. atwlyywwa is the traceability code. ccccc fc-pbga mpcnnnn mmmmm atwlyywwa 85xx notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmm is the 5-digit mask number. atwlyywwa is the traceability code. ccccc tppaaar document number: mpc8541eec rev. 4 12/2006 information in this document is provid ed solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental da mages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or spec ifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2004, 2006. all rights reserved. |
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